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8 months ago

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Timing analysis for Asynchronous part of design

We have a product comprising of multiple FPGAs talking to eachother via MLVDS lines based on bandwidth allocation. The data is shared across on 100MHz MLVDS lines and is asynchronous in nature. The c...

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ShengN_altera
8 months ago
Hi,
If those are asynchronous, you may set false path to the asynchronous input and output check this link https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/setting-timing-constraints-using-the.html

ShengN_altera

Super Contributor

8 months ago

Hi,

If those are asynchronous, you may set false path to the asynchronous input and output check this link https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/setting-timing-constraints-using-the.html

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Timing analysis for Asynchronous part of design

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