Forum Discussion
cjak
Occasional Contributor
5 months agoTiming analysis - long combinational path
Hi, Running Timing Analyzer I get violations due to long combinational paths. Looking at the path in the technology map viewer, it looks like this leftmost block = registerbank holding a config...
sstrell
Super Contributor
5 months agoWithout seeing the code and just going by the names on the logic, you're performing a number of math operations and comparisons on the source signal, adding additional levels of logic. Reviewing and adjusting the RTL code would probably be the easiest solution. Post some code.