Timequest Timing Problems

I assume you have a port called CLK and somehow you are inferring a register, so it gets the name CLK~reg0. That register is then used as the clock of another register. (I'm making a lot of assumptions, so may be wrong).

So first, do you expect CLK~reg0 to exist as a register. Look for it in your RTL or RTL Viewer and see why it's occurring. If it's not supposed to be there, change the code.

If it's correct, see how it's used as a clock. A quick thing I would do in TimeQuest is:

create_clock -name test_clk -period 10.0 {CLK~reg0} ;# This puts a clock constraint on it

report_timing -setup -npaths 100 -detail full_path -to_clock test_clk -panel_name {-> CLK~reg0} ;# This reports timing to this clock, so all destinations use this as a clock.

Now you know what you have, and need to decide how you want to constrian it(e.g. you may want to use create_generated_clock instead of create_clock, I don't know). My guess is that you don't want this register to exist, or to be used as a clock, and it's an RTL change that will fix it.

Thank you！I assigned this port to a register in order to divide frequency. The code is

always@(posedge CLK1)
begin
if(RST1)
 begin
    count <= 0;
    CLK <= 0;
  end
else 
  begin
    if(count == ((N/2)-1))
      begin 
		  CLK <= !CLK; 
		  count <= 6'b0; 
		end
  else
      count <= count + 6'b1;
  end
end

By the way, could you tell me what will you do if you want to divide 50M frequency into 0.5M?

Assuming CLK1 is an input port and you're dividing by 100:

create_clock -period 20.0 -name CLK1 [get_ports CLK1]

create_generated_clock -source CLK1 -divide_by 100 [get_keepers CLK]

Now, I'm guessing CLK is a reg and an output port. Quartus synthesis will name the output port CLK and the internal reg something like CLK~reg. I recommend not name a register and port the same thing, e.g. the divide down register could be CLK_REG and the output CLK:

assign CLK = CLK_REG;

If you do that, assign the generated clock to [get_keepers CLK_REG]