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Honored Contributor
Honored ContributorTimequest Timing Problems
Hi everyone, I got problems when i was using Timequest. My clock name is CLK, but quartus told my that "Warning (332060): Node: CLK~reg0 was determined to be a clock but was found without...
Altera_ForumHonored Contributor
Honored ContributorAssuming CLK1 is an input port and you're dividing by 100:
create_clock -period 20.0 -name CLK1 [get_ports CLK1] create_generated_clock -source CLK1 -divide_by 100 [get_keepers CLK] Now, I'm guessing CLK is a reg and an output port. Quartus synthesis will name the output port CLK and the internal reg something like CLK~reg. I recommend not name a register and port the same thing, e.g. the divide down register could be CLK_REG and the output CLK: assign CLK = CLK_REG; If you do that, assign the generated clock to [get_keepers CLK_REG]
