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Honored Contributor
Honored ContributorTimequest Timing Problems
Hi everyone, I got problems when i was using Timequest. My clock name is CLK, but quartus told my that "Warning (332060): Node: CLK~reg0 was determined to be a clock but was found without...
Altera_ForumHonored Contributor
Honored ContributorThank you！I assigned this port to a register in order to divide frequency. The code is
always@(posedge CLK1)
begin
if(RST1)
begin
count <= 0;
CLK <= 0;
end
else
begin
if(count == ((N/2)-1))
begin
CLK <= !CLK;
count <= 6'b0;
end
else
count <= count + 6'b1;
end
end
