TimeQuest Timing constraint and SDC file

Hello,

I would like to compare two different designs with respect to timing. I do not have any experience working with SDC files. I've gone through online training available at Altera website but I am still not sure if I have done it correctly. I am only concerned about the timing from the input to output pins within the FPGA and I will ignore any delay from outside.

My first design is some inputs that fed into a combinational circuit and the output of this circuit is fed into a register and then the output of the register is fed into another combinational circuit that produces the output. Here is the SDC file I have created:

create_clock -period 10 -name clock [get_ports {clock}]

derive_clock_uncertainty

# virtual clocks

create_clock -period 5 -name clock_in

create_clock -period 5 -name clock_out

set_input_delay -clock { clock_in } -min 0 [get_ports {all input pins}]

set_input_delay -clock { clock_in } -max 0 [get_ports {all input pins}]

set_output_delay -clock { clock_out } -min 0 [get_ports {all output pins}]

set_output_delay -clock { clock_out } -max 0 [get_ports {all output pins}]

I've got negative time when I started the time quest analyser I am not sure what causes those negative time values!

The second design is some inputs that fed into a combinational circuit and the output of this circuit is fed into a ROM and the output is fe into a combinational circuit that generates the output. I did not write any SDC commands yet. I hope someone help me and check the previous SDC file.

I really appreciate any help :)