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Altera_Forum
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11 years ago

TimeQuest Timing constraint and SDC file

Hello, I would like to compare two different designs with respect to timing. I do not have any experience working with SDC files. I've gone through online training available at Altera website b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You have only one set of registers(inputs => logic => registers => logic => outputs. Thus you cannot use dedicated io registers for either inputs or outputs. Since output is failing in your test then try them for outputs after adding another set of registers.