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Altera_Forum
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11 years ago

TimeQuest Timing constraint and SDC file

Hello, I would like to compare two different designs with respect to timing. I do not have any experience working with SDC files. I've gone through online training available at Altera website b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Look at the Data Arrival Path of your first path. 8ns iExt is just the value you put into your set_input_delay -max.

The 0.959ns and 2.642ns are input and output cell delays and won't really change. (You could increase your drive strength maybe)

You go through two LUTs of logic, which is fast. The thing that is variable and hurting you are the two IC(interconnect) delays of 1.631ns and 2.874ns. Note that your input is at X47_Y51 and your output is X95_Y11. So you're going 48 LABs in the X direction and 40 in the Y direction, so that's a pretty long hop. Changing your pinout may help.