Honored ContributorHi All
I successfully finished a full processing analysis for my design circuit, the clock in timeQuest timing analayzer indicate that the (max. freq.=443.07 MHz) where the Restricted FMax. is 250(note; i used the cycloneiii famlly. As listed in the Appendix below) .How can I overcome this problem.
Honored ContributorHonored Contributori think restricted fmax can indicate timing failures in macro timing models. for example, RAM or DSP blocks may have a large black box type of timing model rather than modelling individual paths in the block
as KJ indicated, you can't work around this without rearchitecting (which may mean changing RAM block modes, etc)Honored ContributorHonored ContributorThanks Mr. AndrewS6 for this information . But how can I overcome these forms ( change this Fmax). if i have the cyclone iii kit only.
Honored ContributorI didn't follow exactly what you are trying to achieve. But if you want your design to operate at frequencies higher than 250. Then you have to re-architect it so that the RAM/DSP blocks can be operated at less than 250. Generally, this would mean you have to make that portion of the design operate in parallel with more instances of the same pipeline. But this is not always so, which is what make this problem interesting.
Honored ContributorThanks for your advice . But i need my design to be faster(means higher Fmax) .
Honored Contributoruse an Arria or Stratix
Honored Contributorthak yuo very much mr. thepancake ,i tryaing to do this .
