TimeQuest Issue on CDC Synchronization on Control and Data Path

Hi everybody,

I have an issue on appropriate TimeQuest Constrains on a Clock Cross Domain Design.

My context is an external Synchronous bus with a control signal and a set of data signals:

my design solution is

synchronize the control signal (CS) through a 2 flip-flop metastability filter to produce a related signal (CS_synch) synchronized on the destination domain.

And then use the variation on CS_synch(a falling edge in my case) to determine when to sample stable the external data signals (referred as Data[*] ) on the destination domain as Data_synch[*] .

I don't think that set_false_path could be a comprehensive solution.

The problem is that I suppose that my design works as long as the phase relation between CS and Data[*] is preserved through the routing from the pins to the synchronization destination registers in the FPGA. In other words my design can afford a Data[*] routing path greater than CS path of a specific amount that depends on the internal clock frequecy.

Any suggestion?

I tried with set_max_skew or set_max_delay , but

I'm not sure that any of these is the right way to match delays between multiples routes.

Thanks in Advance for any help!

Claudia

PS: here an extract of my sdc

Solution 1 set_max_delay

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# EXT_BUS cycle time of core_clock, it is also the duration of each state of EXT_BUS EBI fsm (S0,S1 etc)

set EXT_BUS_T_CYC_2_ns 6.7

# EXT_BUS CLKOUT high to chip-select CSn valid

set EXT_BUS_T_CHCV_ns_MAX [expr $EXT_BUS_T_CYC_2_ns + 5]

set EXT_BUS_T_CHCV_ns_MIN 0

# EXT_BUS CLKOUT high to data output (DATA[31:0]) valid (output in S2)

set EXT_BUS_T_CHDOV_ns_MAX 9

# Max delay from EXT_BUS_CSn activation to data output (DATA[31:0]) valid

# Taking as zero reference S0, the min delay for Csn activation and the max delay

# for Data Output valid

set T_CSlow2DOV_MAX [expr $EXT_BUS_T_CYC_ns + 9]

set_max_delay -from [get_ports {DATA[*]}] -to [get_registers {*}] [expr $T_CLK_OSC_ns + $T_CLK_OSC_ns - $T_CSlow2DOV_MAX -$PCB_DELAY_MAX]

Solution 2 set_max_skew only data path

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# Create a max skew constraint that includes only data path arrival

#

set_max_skew -from [get_ports { DATA[*] CS} ] 1 -include { from_clock to_clock clock_uncertainty }

Solution 3 set_max_skew data path + clock path

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# Create a max skew constraint that includes only data path arrival

#

set_max_skew -from [get_ports { DATA[*] CS} ] 1 -include { from_clock to_clock clock_uncertainty }