TimeQuest Issue on CDC Synchronization on Control and Data Path

Thanks a lot Rysc,

from your response I suppose you suggest me that the best way is to use set_max/min_delay.

In my case a transition high low of Cs means a start of a bus transaction,

Data[*] are valid after CS goes low and with a max delay of 22,3 ns, and remain valid until the FPGA closes the transaction with an aknowledge signal.

Data[*] doesn't go through a synchronized couple of flip-flop, but it's sampled when CS_synch goes low.

FPGA internal clock has a 20 ns period .

So I tried to constraint max_delay for Data[*] path,

(being an extra delay on CS path not an issue, instead ... and otherwise I'm not able to

relate delay between two paths !) with :

set_max_delay -from [get_ports {M_DATA_A[*]}] -to [get_registers {*}]

[expr $T_CLK_OSC_ns + $T_CLK_OSC_ns - $T_CSlow2DOV_MAX -$PCB_DELAY_MAX]

# # 20 + 20 - 22.3 - PCB_delay_for_data_lines

Could this be a correct way?

Bye

Claudia