TimeQuest Issue on CDC Synchronization on Control and Data Path

Is Data[*] also going through two synchronization registers, or is it held for multiple clock periods of the resynch clock?

There is a certain class of constraints/circuits that aren't possible in .sdc(and most constraints, as far as I know). The way I would describe them is more of an "algebraic" comparison. For example, let's say you know CS and Data come in at the same time, +/-500ps. Then let's say you sample CS in a 5ns clock domain that is unrelated, so it could latch it by as much as 5ns later if it "just missed". Then you re-sample again for metastability, so another 5ns later. Then you use that output to latch the DATA[*], and you know DATA[*] is held for 12ns. So the CS data delay to the first register + delay from 2nd synchronization register to DATA[*] - delay from DATA[*] to capture register + clock skew must be less than (12-10-0.5). Or something like that. I probably have something wrong, but I have on occasion seen circuits like this which, in theory, would probably work if arbitrary delays could be add/subtracted and compared. It really can't handle this, and I've seen users "get by" with set_max/min_delay constraints that they manually tweak to get rid of what they don't want, or that they subdivide into portions of the sum they can handle.

I'm not positive your circuit falls into this, as I'm not sure how the re-synched CS then determines the capture of DATA[*], but there's a chance that it does. (Sorry I'm not being more helpful)