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Altera_Forum
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12 years ago

TimeQuest Critical Warning using Internal Oscillator (Quartus II)

Hello, I am transitioning away from Xilinx and into Altera. I seem to be having some issues with a critical warning from the TimeQuest Analyzer in Quartus II.

I wrote and compiled a design, and received the warning:

--- Quote Start ---

Critical Warning: Synopsys Design Constraints File file not found: 'PF0086A.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design

--- Quote End ---

I found a lot of information on this error - it seems I can use Quartus II to generate the *.sdc file needed for setting these contraints, for a clean compile. However, there is a little snag. I am using the MegaWizard Plugin to utilize the internal oscillator (per AN-496). So in Quartus, when I go to: "Assignments -> TimeQuest Timing Analyzer Wizard", I cannot enter clock information since this requires an input pin.

I haven't found anything that will help me satisfy the TimeQuest Analyzer using the internal oscillator. (Side note: Leaving the fields in the wizard blank, and just clicking next a few times, created a blank *.sdc file, which quieted the warning - but I think this was more of a hack than a fix.) I've searched the forum, Altera's literature, and google for a solution, but haven't found anything that answers my question.

Does anyone have any recommendations on how to set timing constraints when an internal oscillator is used? Or point me to some literature that explicitly covers this topic?

It's possible I missed something, but I did read through the Quartus II handbook, the TimeQuest Cookbook, the TimeQuest User Guide, and these forums before asking here.

Additional Information:

- Software: Quartus II 12.1 SP 1.33 (32 bit)

- Device: EPM240T100I5N (MAXII)

- Computer: Windows XP (SP3)

- Language: VHDL (1993)

Thank you.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Since you are using an internal oscillator of the MAXII device, you may try the

    derive_pll_clocks

    derive_clock_uncertainty

    commands in your SDC file. I haven't used the internal oscillator in the MAXII but this works with megafunction configured PLL's.

    If those don't work, you can apply the clock setting to the output port of the megawizard function with the

    create_clock command.

    The http://www.altera.com/literature/hb/qts/qts_qii53018.pdf document describes timing quest, which uses the SDC file that is based on the same format used by Synopsys Design Compiler. So once you understand the SDC format, it's actually easier to port from FPGA to ASIC flows.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    @anakha - Thank you very much for your response. Based on your advice, the link you provided, and some poking around the TimeQuest Timing Analyzer report, it seems I was able to properly implement timing constraints for my design.

    Here is the sdc file I created manually - it might not be completely correct (it's clear I still have a long way to go with understanding these tools), but it seemed to get the job done: 

    
#  create clock constraints
create_clock -period 181.818 -name {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc} {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc}
#  create virtual clocks for input/output delay constraints
create_clock -name clock_ext -period 181.818
#  Derive PLL Clocks and Uncertainty
derive_pll_clocks
derive_clock_uncertainty
#  Set input and output delays
set_input_delay -clock { clock_ext } -max 4 
set_input_delay -clock { clock_ext } -min -1 
set_output_delay -clock { clock_ext } -max 6 
set_output_delay -clock { clock_ext } -min -3

    Using the Example 7-7 in the link you provided, I was able to manually create the template for the sdc file. The "create clock constraints" was actually generated by the TimeQuestion Analyzer in the form of warnings: 

    
Critical Warning (332012): Synopsys Design Constraints File file not found: 'PF0086A.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
	Info (332110): create_clock -period 181.818 -name {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc} {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.

    It seems it was not able to automatically generate the required clock signal for constraints, but gave me the starting point of "create_clock -period 181.818 -name {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc} {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc}". "osc" is the name of my internal oscillator, so this looked promising.

    Creating the virtual clock was recommended in the link you provided, as well as setting the input and output delay. Table 7-2 showed me the arguments to use to access all the input and output pins at once for these delay arguments.

    After including the sdc file at the top of this post, I was able to compile and there were no longer any "unconstrained path" warnings from the TimeQuest Analyzer.

    I really appreciate your help with this! Thank you very much.