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Altera_Forum
Honored Contributor
12 years agoSince you are using an internal oscillator of the MAXII device, you may try the
derive_pll_clocks derive_clock_uncertainty commands in your SDC file. I haven't used the internal oscillator in the MAXII but this works with megafunction configured PLL's. If those don't work, you can apply the clock setting to the output port of the megawizard function with the create_clock command. The http://www.altera.com/literature/hb/qts/qts_qii53018.pdf document describes timing quest, which uses the SDC file that is based on the same format used by Synopsys Design Compiler. So once you understand the SDC format, it's actually easier to port from FPGA to ASIC flows. Pete