TimeQuest Critical Warning using Internal Oscillator (Quartus II)

@anakha - Thank you very much for your response. Based on your advice, the link you provided, and some poking around the TimeQuest Timing Analyzer report, it seems I was able to properly implement timing constraints for my design.

Here is the sdc file I created manually - it might not be completely correct (it's clear I still have a long way to go with understanding these tools), but it seemed to get the job done:

#  create clock constraints
create_clock -period 181.818 -name {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc} {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc}
#  create virtual clocks for input/output delay constraints
create_clock -name clock_ext -period 181.818
#  Derive PLL Clocks and Uncertainty
derive_pll_clocks
derive_clock_uncertainty
#  Set input and output delays
set_input_delay -clock { clock_ext } -max 4 
set_input_delay -clock { clock_ext } -min -1 
set_output_delay -clock { clock_ext } -max 6 
set_output_delay -clock { clock_ext } -min -3 

Using the Example 7-7 in the link you provided, I was able to manually create the template for the sdc file. The "create clock constraints" was actually generated by the TimeQuestion Analyzer in the form of warnings:

Critical Warning (332012): Synopsys Design Constraints File file not found: 'PF0086A.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
	Info (332110): create_clock -period 181.818 -name {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc} {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.

It seems it was not able to automatically generate the required clock signal for constraints, but gave me the starting point of "create_clock -period 181.818 -name {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc} {osc_inst|osc_altufm_osc_518_component|maxii_ufm_block1|osc}". "osc" is the name of my internal oscillator, so this looked promising.

Creating the virtual clock was recommended in the link you provided, as well as setting the input and output delay. Table 7-2 showed me the arguments to use to access all the input and output pins at once for these delay arguments.

After including the sdc file at the top of this post, I was able to compile and there were no longer any "unconstrained path" warnings from the TimeQuest Analyzer.

I really appreciate your help with this! Thank you very much.