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Hi Pletz
No, I don't re-synchronize the reset signal. My thought was that it's pointless to synchronyze it, as the reset of the state machines and FIFOs are asynchronous anyway. Do you think this may cause problems?
I could wrap the state machines in a if-structure. Is this a good way to make a synchronous reset?
-- reset is asynchronous signal from other block
state.clk = clk;
if
-- synchronize reset with clock of machine
dff(reset, clk)
then
state = s0;
else
case state is
when s0 =>
...
when s1 =>
...
when s2 =>
...
end case;
end if;
At the time I am simply using the asynchronous reset input of the machine:
state.clk = clk;
state.reset = reset;
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Hi,
are you using AHDL ? I'm not very familiar with the language, but I would resync the reset
with a DFF outside the statemachine. Are all statemachines as fullcase implemented ?
no illegal states ?
Kind regards
GPK
Honored Contributor
