Timequest and Async Paths

I included an updated diagram, responses:

1) Is the source of AsyncIn really asynchronous to the clock?

-Yes

2) Is the destination of AsyncOut really asynchronous to the clock?

-Yes

3) And if so, what is the purpose of the clocked logic?

-The diagram is a VERY simplified representation (updated below), the clocked logic is used to implement async 2-to-1 muxes in series, gate off set while the latch is being reset, etc. I want to be sure if I am configuring muxes or resetting latches that I do not say my configuration is complete until some amount of time afterwards so my async logic does not glitch. Therefore I use a 2-to-1 mux on the latch set lines and the async output to enforce this and I need to constrain the prop delay from the flop to make sure the assumption for gating off it met.

4) BTW, trying to constrain a delay to be exactly X ns is not possible due to PVT variations. You can only constrain to a range.

- Correct, I am looking for a 0-33ns range