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Altera_Forum
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13 years ago

Timequest and Async Paths

Hello: I have a simple CPLD design that has an async input pin that goes to a latch. From the latch it goes to an async output pin. I would like to constrain the input path from the pin to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I have tried the virtual clocks and I can keep trying. To help I made a simple diagram representing what I am doing. I am setting up 2-to-1 LCELLs to do async logic glitchless and then I have a SR-LATCH implemented in a LUT to control my logic. It must be async and I verified with the floorplanner.

I want to constrain the path from the flop's clock to out, through its routing delay to the LCELL, through the LCELL and ultimately to the SR-LATCH to be one clock period- 33ns. I then desire the Async in through the input delay through the LCELL, and then through the routing to the SR-LATCH to be 33ns as well. Finally the LCELL output routed to the pin (maybe through more LCELLS) to also be 33ns. How do I do this with virtual clocks? I will try some of your suggestions as well. Let me know of any suggestions. Thanks!