Time Quest: Fail Setup Time n etc

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Hi. I just switch from classic timing analysis(CTA) to time quest analysis(TQA).

Some steps are performed(as in TimeQuest Timing Analyzer.pdf) to do switching on timing analysis. After sdc file is generated, i din add any constraint into it as i totally have no idea what value to be added.

FYI, When perform full compilation on CTA, everything is fine.

However, in TQA, a lot of cases fail like

Slow Model: setup, minimum pulse width and worst case timing

Fast Model: minimum pulse width and worst case timing.

FYI, In simulation, it still get the expected result. Wonder why though it fails.

I try using the timing advisor and do as it instruct me. Anyhow, it does not solve the problem.

Any idea on how to solve it?

thanks

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Hi,

without more informations it is difficult to help you. First you should look to the clocks which TimeQuest detected. TimeOuest assumes that all clocks are related as default.

That is different to the Classic Timing Analyzer. Cut all paths between unrelated clock domains and re-run the Timing analysis.

Kind regards

GPK

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Hi. I have no idea how to describe the details to you. However, i will attach the verilog and sdc file.

Pls have a look on it. May you show or guide me on how to write sdc file?

FYI, i just want to do timing simulation without any pin assignment.

thanks a lot

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Hi,

your create_clock command was not correct, therefore TimeQuest uses the default

clock of 1GHz. I have a new SDC file attached.

Kind regards

GPK