Time out problem

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_test is
port (
    CLOCK_50MHz: in std_logic;
    fin: out bit;
    );
end entity counter_test;
 
architecture behav of counter_test is    
            
    signal fin: bit := '0';
    
    begin    
    
    process (CLOCK_50MHz)
--        variable sub_cnt : integer := 0;
        constant timeout:time:=10 ms; 
    begin  
        if (CLOCK_50MHz'event and CLOCK_50MHz = '1')then
            cnt <= '1' after timeout; 
--            sub_cnt := sub_cnt + 1;
            end if;
--    wait until (CLOCK_50MHz'event and CLOCK_50MHz = '1') for timeout;
            
    end process; 
        
end architecture behav;

I am trying to make a synthesizable code. I made some mistakes in the previous code, now I changed it but it still doesn't work. I can compile it but the reault after simulation is not what I'm expecting. I am totally confused about how to impelement a time limitration here. I am using QuartusII, and that software doesn't support "wait for"......