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I am trying to make a synthesizable code. I made some mistakes in the previous code, now I changed it but it still doesn't work. I can compile it but the reault after simulation is not what I'm expecting. I am totally confused about how to impelement a time limitration here. I am using QuartusII, and that software doesn't support "wait for"......
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Hi,
I suggest you to have a look at
quartus vhdl templates (there are counter examples I think) and a get a good book (or tutorials or good examples) about synthesizable VHDL code.
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=coding%20style "wait until" "after" are ignored by Quartus synthesizer.
Have a nice day.
Honored Contributor
