"The VHDL code for resetting the release IP is not functioning as expected."

Hello,

I am currently working on designing a straightforward VHDL test for an Agilex 7 m-series FPGA and have encountered a hurdle. Specifically, I am in the process of creating a Reset Release IP code snippet and have been experiencing difficulty in determining the correct approach. I've made attempts to work with the code demonstrated in the RRIP video, but I'm unsure about the IP's internal declarations. I've attached my code along with the errors I've encountered. Your assistance in this matter would be greatly appreciated.

Thank you,

Drew