Honored ContributorHi!
I want ot use the Modelsim with Quartus to simulate,but there are some errors. I used the Quartus to create a Testbench Template and modify it,And I modified the setting of the Quartus,then the Modelsim launched automatically after clicking the button of start compilation.but there are some problems that I can't solve. Is there any one can help me? Thank you in advance!
Honored Contributordid RTL simulation work OK?
Honored ContributorYes,it works well.
But why did the Modelsim can't work if I click the start compilation? thanks!Honored Contributori got the same problem.And i got no idea to solve this problem.Hope anyone can give a help!
Honored ContributorHi!
I have solved this problem,in the Edit Testbench Setting the top level module in test bench and design instance name in testbench must full in the name of entity,they should be the same. there is always a problem about the SDF file when use the vhdl,but that will not occurs if use the verilog.Honored ContributorYour testbench seems to be ok,maybe the period is too short result to the device does not work.
by the way,you could use the Quartus II to generate the testbench template.Honored Contributor@Lewis: have you resolved?
I've the same problem: RTL works, whereas Gate-level firstly had the "Failed to find INSTANCE" problem and after renaming settings I've that all stimulus do not move (seems as Modelsim do not use the testbench file) I've the test bench module that is : tb_top.vhd My quartus II v10sp1 design top is: top.vhd In attachment you can find the 2 .vhd files and an image of the settings of simulator. If some can help I'll be pleased. Best regardsHonored ContributorOk I've done, the problem was in the configuration of the TestBench.
You must set on setting / Simulator /Test Bench: - Name: a name that you want for your test bench (can be anything) - Top Level Module: the name of the Entity of the Test Bench - Design instance name in test bench: the name of the declarated component (in my case was uut) - of course you've to add your test bench file under file name: (brouse it) in my case was tb_top.vhd Hope it helps someonelseHonored ContributorHey Darkwave!You're right!
I found this main problem is the design instance name in testbench in the configuration of the TestBench. design instance name in testbench must be the name of declared component. But not the name of the component!
