New ContributorThe Jitter issue on the SDI 12G project (Quartus 20.1)
Hello, we’re facing the following problem.
We’re developing the project with SDI 12G output signal on base Cyclone 10 GX FPGA.
We use the Intel IP for SDI protocol, Transceiver PHY and Tx PLL. Here you can see the common architecture of the project:
It works well, but sometimes we get bad jitter performance on the 12G output. It happens when we do the Tx PLL recalibration process.
After recalibration finished we can get either good jitter (less than 0.21 UI) or bad one (more than 0.3 UI).
We don’t know what it depends on. The recalibration process is the same and there aren’t any differences between cases.
Accordingly to the Intel Cyclone GX 10 Transceiver PHY User Guide (UG20070) we tried to improve jitter following next steps:
- Use ATX PLL instead of fPLL because ATX PLL has better jitter performance;
- Set Transmitter High-Speed Compensation option to Enable for corresponding Tx serial data out pin.
But no one of these steps helped us.
Could you give us any advice what else we can do to influence jitter performance, please?
