New Contributor
Regular ContributorHi,
As I understand it, you have some inquiries related to the jitter performance with the 12G SDI TX output in C10GX device. For your information, the following are the possibilities that I could think of for your reference:
1. Input refclk - Potential SI or jitter problem at the input refclk would propagate into the TX PLL and then impact the TX output jitter. It is recommended for you to measure the eye diagram using oscilloscope at the FPGA input refclk to check if there is any anomaly.
2. Dedicated input refclk - The dedicated input refclk pin for the transcevier will have the best performance as compare to other type of refclk input ie RX pin, refclk network. You can try to switch to dedicated input refclk pins if you are not using them currently.
3. Just to check if you are running a single channel SDI TX or if you have multiple channels? If there are multiple channels, it is recommended to try with single channel only to see if things improve to narrow down any potential crosstalk problem.
4. Just to check if the TX PLL refclk and the CLKUSR are directly sourced from on-board free running and stable oscillators? This is the ensure successful power up calibration for TX PLL and transceiver channel.
5. If you are using ATX PLL, you can try with different Bandwidth setting to see if there is any difference.
Please let me know if there is any concern. Thank you.
