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Altera_Forum
Honored Contributor
Honored ContributorTestbench
Hi everyone
I need to help for my graduate thesis. I am working on aes 128 cipher and i had a code but i need a simulation and testbench . how can i do them . pls help me . I appretiated for your advice and help I hope I could tell you thanks.9 Replies
Altera_ForumWhat have you tried so far, and what problems are you having?
- Altera_Forum
my ports are
entity key_gen is port (roundkey: in STD_LOGIC_VECTOR(127 downto 0); round: in round_type; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end entity key_gen; I need to testbench code for modelsim simulation. - Altera_Forum
And whats the problem?
- Altera_Forum
I had a aes code but i dont know that is it works correct. I need to testbench code for check my code. can you control my code and faults? I am a beginner at fpga
my code's here - Altera_Forum
Why not try writing a testbench yourself, and come back when you have problems?
- Altera_Forum
i am trying to write but i am not so good. and I have to 2 weeks for project ending.
- Altera_Forum--- Quote Start --- i am trying to write but i am not so good. and I have to 2 weeks for project ending. --- Quote End --- Well, have a go, then come back when you are having problems. We can help with problems, not do your work for you.
- Altera_Forum
i have to a few error at testbench code.. can anyone help me?
- Altera_Forum
You have no "begin" after architecture.
"variable" cannot be used in architectures, they have to be in processes/functions (did you mean signal?)
