Honored ContributorHi everyone
I need to help for my graduate thesis. I am working on aes 128 cipher and i had a code but i need a simulation and testbench . how can i do them . pls help me . I appretiated for your advice and help I hope I could tell you thanks.
Honored ContributorWhat have you tried so far, and what problems are you having?
Honored Contributormy ports are
entity key_gen is port (roundkey: in STD_LOGIC_VECTOR(127 downto 0); round: in round_type; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end entity key_gen; I need to testbench code for modelsim simulation.Honored ContributorAnd whats the problem?
Honored ContributorI had a aes code but i dont know that is it works correct. I need to testbench code for check my code. can you control my code and faults? I am a beginner at fpga
my code's hereHonored ContributorWhy not try writing a testbench yourself, and come back when you have problems?
Honored Contributori am trying to write but i am not so good. and I have to 2 weeks for project ending.
Honored ContributorHonored Contributori have to a few error at testbench code.. can anyone help me?
Honored ContributorYou have no "begin" after architecture.
"variable" cannot be used in architectures, they have to be in processes/functions (did you mean signal?)
