Altera_Forum
Honored Contributor
Honored Contributortestbench
I wonder what is wrong when i drive modelsim...
here is the testbench code. :confused: -- Generated on "10/05/2012 12:26:11" -- Vhdl Test Bench template for design : uppgift_3b -- -- Simulation tool : ModelSim-Altera (VHDL) -- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY uppgift_3b_vhd_tst IS END uppgift_3b_vhd_tst; ARCHITECTURE uppgift_3b_arch OF uppgift_3b_vhd_tst IS -- constants -- signals SIGNAL addr_ram : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL addr_rom : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL clk : STD_LOGIC:='0'; SIGNAL data_ram : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL q_ram : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL q_rom : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL we_ram : STD_LOGIC; COMPONENT uppgift_3b PORT ( addr_ram : IN STD_LOGIC_VECTOR(2 DOWNTO 0); addr_rom : IN STD_LOGIC_VECTOR(1 DOWNTO 0); clk : IN STD_LOGIC; data_ram : IN STD_LOGIC_VECTOR(2 DOWNTO 0); q_ram : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); q_rom : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); we_ram : IN STD_LOGIC ); END COMPONENT; BEGIN i1 : uppgift_3b PORT MAP ( -- list connections between master ports and signals addr_ram => addr_ram, addr_rom => addr_rom, clk => clk, data_ram => data_ram, q_ram => q_ram, q_rom => q_rom, we_ram => we_ram ); clk<= not(clk) after 20 ns; init : PROCESS -- variable declarations BEGIN WAIT FOR 100ns; addr_ram <= "01"; WAIT FOR 100ns; addr_rom <= "10"; WAIT FOR 100ns; data_ram <= "011"; WAIT FOR 100ns; we_ram <= "1"; -- code that executes only once WAIT; END PROCESS init; END uppgift_3b_arch;
