testbench

# Reading C:/altera/12.0/modelsim_ase/tcl/vsim/pref.tcl # do uppgift_3b_run_msim_rtl_vhdl.do # if {[file exists rtl_work]} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Copying c:\altera\12.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# ** Warning: Copied c:\altera\12.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.# Updated modelsim.ini.# # vcom -93 -work work {C:/altera_trn/VHDL_kurs/uppgift_3b/uppgift_3b.vhd}# Model Technology ModelSim ALTERA vcom 10.0d Compiler 2012.01 Jan 18 2012# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package NUMERIC_STD# -- Loading package std_logic_arith# -- Loading package STD_LOGIC_UNSIGNED# -- Compiling entity uppgift_3b# -- Compiling architecture BLOCK_RAM_ROM_FPGA of uppgift_3b# # vcom -93 -work work {C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht}# Model Technology ModelSim ALTERA vcom 10.0d Compiler 2012.01 Jan 18 2012# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity uppgift_3b_vhd_tst# -- Compiling architecture uppgift_3b_arch of uppgift_3b_vhd_tst# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(72): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(74): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(76): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Warning: [4] C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(78): (vcom-1207) An abstract literal and an identifier must have a separator between them.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(79): String literal found where non-array type ieee.std_logic_1164.STD_LOGIC was expected.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(73): (vcom-1272) Length of expected is 3; length of actual is 2.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(85): VHDL Compiler exiting# ** Error: c:/altera/12.0/modelsim_ase/win32aloem/vcom failed.# Error in macro ./uppgift_3b_run_msim_rtl_vhdl.do line 10# c:/altera/12.0/modelsim_ase/win32aloem/vcom failed.# while executing# "vcom -93 -work work {C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht}"#