testbench

BEGIN

-- test protokoll case 1

WAIT FOR 100ns;

addr_ram <= "01";

-- test protokoll case 2

WAIT FOR 100ns;

addr_rom <= "10";

-- test protokoll case 3

WAIT FOR 100ns;

data_ram <= "011";

-- test protokoll case 4

WAIT FOR 100ns;

we_ram <= '1';

-- code that executes only once

WAIT;

END PROCESS init;

END uppgift_3b_arch;

i have this

# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(75): (vcom-1272) Length of expected is 3; length of actual is 2.# ** Error: C:/altera_trn/VHDL_kurs/uppgift_3b/simulation/modelsim/uppgift_3b.vht(97): VHDL Compiler exiting# ** Error: c:/altera/12.0/modelsim_ase/win32aloem/vcom failed.