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Altera_Forum
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15 years ago

Testbench in Modelsim problem: no signal clear in a loop

Hi, I'm doing a project that writes text in a VGA. I'm doing the testbench to try everything, and i want to generate the rows and columns of my VGA with the testbench, i need it to know which p...
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Altera_Forum
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15 years ago

Thank you very much for your response, now, is working!!!!

Is there any advantage of not using a proces for the clock generation? And, any advantatge of using variables instead of signals and the wait?

Thank you!!!