Testbench in Modelsim problem: no signal clear in a loop

My Comments next to your code

--Clock generation:
        gen_clock : process(Clck)    
            begin
                Clck <= not Clck after PERIOD1/2;
        end process;

This does not need to be in a process. It works fine as a line outside.

--Row & Column generation for the system                
        gen_col_row : process
               begin
                    nReset<='0';    
                    wait for PERIOD1;
                    nReset<='1';
                    
                    Columna<=(others=>'0');    --Initialize counters 
                    Fila<=(others=>'0');    
                    
                    wait until ((Clck'event) AND (Clck='1'));    --Clock synchronization
                    
                    for i in 1 to 528 loop    --Generates Fila(Row)
                        for j in 1 to 800 loop    --Generates Columna(Column)
                            Columna<=Columna+'1';--Columna = column in spanish...
                            
                            wait for PERIOD1;
                            
                        end loop;
                        
                        Columna<=(others=>'0'); --THIS DOESN'T WORK!!!!!!
                        Fila<=Fila+'1';--Fila=Row in spanish....
                    end loop;
        end process;

You need to wait after Fila <= Fila + 1; otherwise it goes straight back into the next loop, and with no wait, the column <= '0' is overridden with the column <= column + 1;

To fix this either:

1. after fila <= fila + 1; put wait for 0ns; (this causes the simulator to skip 1 delta cycle, and will set columna to 0;

2. Use variables instead of signals for row and column instead. They are updated immediatly and you wont have this problem.