New ContributorTest stimulus for FPGA validation
Hello,
I am trying to do test validation for my project and was wondering how to implement a test stimulus.
I want to make clear I am not wanting to functionally verify such as using a testbench for ModelSim - as I have already done this.
What I want to see is if the signals actually behave the same way after being implemented in the FPGA
My intuition is using SignalTap as it allows us to track signals on an FPGA.
However, my only experience with it is seeing push buttons and triggers.
Even the ISSP, if I recall correctly, requires manual tuning of the signals bit by bit using force commands - I dont think this is really efficient for large scale.
My code is a finite state machine that relies on certain inputs and is synchronous to a clock.
Is providing a test stimulus something simple I am missing or does require some script or something?
PS - I notice that there is a system memory content editor but I dont know if this is what I really want.
Thank you
The tools you mention are all for on-chip debugging with the design running in hardware. This seems to be what you want to do.
If you are saying you want to toggle internal signals while the design is running, then ISSP is what you want. You can use it along with Signal Tap to see more high-speed signaling as you toggle signals (ISSP probe data is only available as fast as the JTAG connection). You can set up a Signal Tap trigger based on the ISSP source toggling or anything else that should be happening while the design is running.
In-System Memory Content Editor is for viewing and editing the contents of on-chip RAM blocks during runtime. That doesn't seem like what you want.
