test bench

You must change your two processes:

• Make a process for the clock:

Clock_Process: PROCESS
BEGIN
  clock <= '0';
  WAIT FOR 50 ns;
  clock <= '1';
  WAIT FOR 50 ns;
  -- Do not put 'WAIT;' as it will force the process
  -- to wait forever and consequently, clock will never toggle.
END PROCESS;

• Make a process for the reset:

Reset_Process: PROCESS
BEGIN
  Resetn <= '0'; -- Active low reset
  WAIT FOR 201 ns;  -- Maintain low reset during 201ns
  Resetn <= '1';  -- Release resetn
  WAIT;
END PROCESS;

• Make a process for the input data:

always : PROCESS                                             
-- optional sensitivity list                                  
( clock  )                                                 
BEGIN                                                         
  -- code executes for every event on sensitivity list 
  carry_in <= '0';  -- First carry_in value (input of your block)
  D <= "1101";   -- First D value (input of your block)
  wait for 300ns;
  wait until rising_edge(clock); -- wait until rising edge of clock
  wait for 1ns; -- Just to model the Tco of flip-flop
  carry_in <= '0';  -- Second carry_in value (input of your block)
  D <= "1101"; -- SecondD value (input of your block)
  wait;  -- You can use this as this is the last data of your test bench
END PROCESS always;

Thank you very much( mr.adouville) for the code you sent to me, The program did not work (when i cheeked by run analysis &elaboration process's) because of the WAIT state( may be it must to change the type of file for another HDL file . Please if you can to help mi or give any advice to resolve this problem

you cant have wait statements f you have a sensitivity list. delete the sensitivity list on a process with wait statements in.

Hi thanks for advice, but when i delete the sensitivity list then i cant processed the code, i try this way.,but no progress

 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Block4CLA_vhd_tst IS
END Block4CLA_vhd_tst;
ARCHITECTURE Block4CLA_arch OF Block4CLA_vhd_tst IS
    -- constants
    constant CLOCK_PERIOD:  time := 100 ns;
    -- signals
    SIGNAL carry_in : STD_LOGIC;
    SIGNAL clock : STD_LOGIC := '0';
    SIGNAL Cout : STD_LOGIC;
    SIGNAL D : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL Resetn : STD_LOGIC;
    signal Sim_Complete: std_logic := '0';
BEGIN
 i1 : entity work.Block4CLA
 PORT MAP
    (
        -- list connections between master ports and signals
     carry_in => carry_in,
     clock    => clock,
     Cout     => Cout,
     D        => D,
     Q        => Q,
     Resetn   => Resetn
 );
    clock <- not(clock) and not(Sim_Complete) after (CLOCK_PERIOD / 2);
    Resetn <= '0', '1' after 201 ns;
    Main : process
    begin
        d <= "0000";
        carry_in <= '0';
        wait until (Resetn = '1') and rising_edge(Clock);
        for c in 0 to 1 loop
            if (c = 0) then
                carry_in <= '0';
            else
                carry_in <= '1';
            end if;
            for d_loop in 0 to 15 loop
                d <= std_logic_vector(to_unsigned(d_loop, d'length));
                wait until rising_edge(clock);
                -- Add assertions here to check that the outputs Q and Cout are correct
            end loop;
        end loop;
        Sim_Complete <= '1';
        wait;
    end process Main;
END Block4CLA_arch;

Hello sir

Hello sir

you cannot compile this code in quartus. For a start, you have no inputs or outputs, so Quartus will simply compile it all away to nothing. And secondly - quartus is NOT a application designed for testing. You need to use something like modelsim.

Hello