test bench

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Hi thanks for advice, but when i delete the sensitivity list then i cant processed the code, i try this way.,but no progress

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You should consider being more specific about what you mean...it's totally unclear about where you're having problems. Below is some code (untested, not even compiled, up to you to fix) that will generate the stimulus to test your widget

 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY Block4CLA_vhd_tst IS
END Block4CLA_vhd_tst;
ARCHITECTURE Block4CLA_arch OF Block4CLA_vhd_tst IS
    -- constants
    constant CLOCK_PERIOD:  time := 100 ns;
    -- signals
    SIGNAL carry_in : STD_LOGIC;
    SIGNAL clock : STD_LOGIC := '0';
    SIGNAL Cout : STD_LOGIC;
    SIGNAL D : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL Resetn : STD_LOGIC;
    signal Sim_Complete: std_logic := '0';
BEGIN
 i1 : entity work.Block4CLA
 PORT MAP
    (
        -- list connections between master ports and signals
     carry_in => carry_in,
     clock    => clock,
     Cout     => Cout,
     D        => D,
     Q        => Q,
     Resetn   => Resetn
 );
    clock <- not(clock) and not(Sim_Complete) after (CLOCK_PERIOD / 2);
    Resetn <= '0', '1' after 201 ns;
    Main : process
    begin
        d <= "0000";
        carry_in <= '0';
        wait until (Resetn = '1') and rising_edge(Clock);
        for c in 0 to 1 loop
            if (c = 0) then
                carry_in <= '0';
            else
                carry_in <= '1';
            end if;
            for d_loop in 0 to 15 loop
                d <= std_logic_vector(to_unsigned(d_loop, d'length));
                wait until rising_edge(clock);
                -- Add assertions here to check that the outputs Q and Cout are correct
            end loop;
        end loop;
        Sim_Complete <= '1';
        wait;
    end process Main;
END Block4CLA_arch;

Kevin Jennings