test bench from a program

how the test bench to run this program on ModelSim Altera?

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity clkdiv is

generic ( n : integer :=10);

port (

clkin : in std_logic;

clkout : out std_logic);

end clkdiv;

architecture arc of clkdiv is

signal clk_tmp : std_logic := '0';

signal cnt : integer := 0 ;

begin

process (clkin,cnt) begin

if (clkin'event and clkin='1') then

cnt <= cnt + 1;

if ( cnt = n-1 ) then

clk_tmp <= not clk_tmp;

cnt <= 0;

end if;

end if;

end process;

clkout <= clk_tmp ;

end arc;