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Altera_Forum
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16 years ago

test bench from a program

how the test bench to run this program on ModelSim Altera? library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity clkdiv i...
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Altera_Forum
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16 years ago

You just need a process that generates the clock for the clkin port. Any good tutorial or book about VHDL simulation should tell you how to do it.