tco time question

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Hi,

i'm currently developing a binary counter (256 bits) into a MAX II CPLD using Quartus II and i have a question.

When i start the Classic Timing analyzer the result for tco is 11.027 ns.

What is this time?

Imagine that the counter is in this state "011111111...111" (left bit is MSB), is the tco time the delay between a rising edge (the counter up on rising edge) clock and the MSB bit to go to "1"? After that time all output lines are stable in a valid state?

Thank you.

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Tco is time after that the output signals are stable, related to the clock input.

Kind regards

GPK

Okay but the Classic Timing analyzer check the situation when i use a counter? Check all timing with 2^256 clock edges?

I must be sure.

Tco for a flipflop is the time from clock edge to the transition of Q output (Q being decided for that clk edge).

That is internal Tco. Altera reports it as external Tco i.e. time from clk pin to output pin of register which is more relevant practically.

The report gives Tco for every path. So your counter should have 8 Tco values(one for every bit, not just MSB).

Tco is not a constraint but is used to achieve correct Tsetup or Th of external chip registers.

are you saying 256 bit counter. This is huge. on 50MHz it will probably take thousands of years to finish to roll over, till doom's day

Hold on, probably millions of years !!!

each clk of 50 MHz = 1/50 microsec

microsec to maximum value of counter = 2^256*(1/50)

= that divided by (10^6 *60*60*24*365) in years, check on your calculator