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Hi,
i'm currently developing a binary counter (256 bits) into a MAX II CPLD using Quartus II and i have a question.
When i start the Classic Timing analyzer the result for tco is 11.027 ns.
What is this time?
Imagine that the counter is in this state "011111111...111" (left bit is MSB), is the tco time the delay between a rising edge (the counter up on rising edge) clock and the MSB bit to go to "1"? After that time all output lines are stable in a valid state?
Thank you.
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Tco is time after that the output signals are stable, related to the clock input.
Kind regards
GPK
Honored Contributor
