Tco in Max II family

Most likely you have not set up your constraints correctly.

Read this document and look at the associated constraints files:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.zip

Examples of MAX II Tco from that document are:

Info: TIMEQUEST: Slow process corner timing:
Info: TIMEQUEST: spi_sck : tco = 4.705 ns
Info: TIMEQUEST: spi_mosi: tco(min) = 5.397 ns, tco(max) = 5.926 ns
Info: TIMEQUEST: Fast process corner timing:
Info: TIMEQUEST: spi_sck : tco = 2.096 ns
Info: TIMEQUEST: spi_mosi: tco(min) = 2.532 ns, tco(max) = 2.898 ns

i.e., between 2ns and 6ns.

Cheers,

Dave

I dont have timing constraints, then recommendation is setup timing constrains with tco=4.6ns? Ok, any way using constraints is no guaranteed to reach tco=4.6ns, true ?

and second: what really means the tco value listed in Max II handbook ?

Thanks.

Note: Im new in this, I'm implementig a design that calculates an output (using an equation) from one input data where a clk signal indicates a new input data , and Im tryng to determine the time in what I have a valid output after a positive edge clock.

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I dont have timing constraints

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Then that tells the tool "I don't care", so it does not try :)

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then recommendation is setup timing constrains with tco=4.6ns?

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That is not quite how timing constraints work. You need to tell the synthesis tool "what is the 'latest' a signal can arrive at the external device that output pin is connected to". If that value is 4.6ns, then you need to provide the appropriate timing parameters as TimeQuest constraints. The document I linked to has images that show you how to describe your timing requirements, and Rsync has documents on the AlteraWiki that also describe the procedures.

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Ok, any way using constraints is no guaranteed to reach tco=4.6ns, true ?

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You would have to constrain the tool and see.

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and second: what really means the tco value listed in Max II handbook ?

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Absolutely nothing. Marketing probably just wanted a number to have in the handbook :)

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Note: Im new in this, I'm implementig a design that calculates an output (using an equation) from one input data where a clk signal indicates a new input data , and Im tryng to determine the time in what I have a valid output after a positive edge clock.

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Look at the timing diagrams in the PDF above. Draw timing diagrams for your application. Look at the TimeQuest constraints scripts in the zip file listed above, and create an equivalent version for your application. This will help you determine the maximum operating frequency for your design.

As Rsync commented, you need to make sure your design is "pipelined", i.e., include input registers, output registers, and internal data processing registers where appropriate. This allows the synthesis tool to move the logic around inside the device while its trying to meet your timing goal.

Cheers,

Dave