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Altera_Forum
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12 years ago

Tco in Max II family

Hi, I'm working on a verilog design and I want to measure the clock to output time (Tco) in this design using MAX II EPM2210F324I5 device. The value of Tco using timequest timing analyzer ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Most likely you have not set up your constraints correctly.

Read this document and look at the associated constraints files:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.zip

Examples of MAX II Tco from that document are: 


Info: TIMEQUEST: Slow process corner timing:
Info: TIMEQUEST: spi_sck : tco = 4.705 ns
Info: TIMEQUEST: spi_mosi: tco(min) = 5.397 ns, tco(max) = 5.926 ns
Info: TIMEQUEST: Fast process corner timing:
Info: TIMEQUEST: spi_sck : tco = 2.096 ns
Info: TIMEQUEST: spi_mosi: tco(min) = 2.532 ns, tco(max) = 2.898 ns

i.e., between 2ns and 6ns.

Cheers,

Dave