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Altera_Forum's avatar
Altera_Forum
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12 years ago

Tco in Max II family

Hi, I'm working on a verilog design and I want to measure the clock to output time (Tco) in this design using MAX II EPM2210F324I5 device. The value of Tco using timequest timing analyzer ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I dont have timing constraints, then recommendation is setup timing constrains with tco=4.6ns? Ok, any way using constraints is no guaranteed to reach tco=4.6ns, true ?

and second: what really means the tco value listed in Max II handbook ?

Thanks.

Note: Im new in this, I'm implementig a design that calculates an output (using an equation) from one input data where a clk signal indicates a new input data , and Im tryng to determine the time in what I have a valid output after a positive edge clock.