Tcl Error in Timing Analysis phase using LVDS SERDES RX IP

Hi,

the solution worked for me in Quartus 19.3 as well. See more info https://forums.intel.com/s/question/0D70P000006iNdK/tcl-error-error-argument-nodeobject-is-an-object-filter-that-matches-no-objects-specify-one-matches-only-one-object-when-using-lvds-serdes-ip

I also used a similar solution in the "altera_lvds_core20_191\synth\lvds_rx_altera_lvds_core20_191_5u346cy.sdc" file to get rid of some warning messages.

I replaced

set pll_fclk_tree_name "${lvds_clock_tree_inst_name}|lvdsfclk_in"

with

foreach_in_collection lvds_node [get_nodes -nowarn "$lvds_instance_name|*|fclk"] { set pll_fclk_tree_name [get_node_info -name [get_edge_info -src [get_node_info -clock_edges [lindex $lvds_node 0]]]]; break }

and

set pll_lden_tree_name "${lvds_clock_tree_inst_name}|loaden_in"

with

foreach_in_collection lvds_node [get_nodes -nowarn "$lvds_instance_name|*|loaden"] { set pll_lden_tree_name [get_node_info -name [get_edge_info -src [get_node_info -clock_edges [lindex $lvds_node 0]]]]; break }

Regards

Michael