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zener's avatar
zener
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

SystemVerilog type parameters not supported in Quartus Lite?

I found that SystemVerilog modules which I can simulate in Questa, Synopsys VCS, Vivado xsim and Verilator, synthesize in Vivado (free version) and Quartus Pro does not synthesize in Quartus Lite. I...
Hdl
zener's avatar
zener
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

This is somewhat problematic as I can't use utility libraries like pulp-platform with Quartus Std/Lite:

https://github.com/pulp-platform/common_cells/blob/master/src/shift_reg.sv

It might be possible to use various pre-processors to compile SystemVerilog-2012 into plain Verilog or older SystemVerilog versions, but this requires modification to the current flow.

Even professional users with a Pro license might want to re-use their verified RTL libraries when targeting low end devices.