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zener's avatar
zener
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

SystemVerilog type parameters not supported in Quartus Lite?

I found that SystemVerilog modules which I can simulate in Questa, Synopsys VCS, Vivado xsim and Verilator, synthesize in Vivado (free version) and Quartus Pro does not synthesize in Quartus Lite. I...
Hdl
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
10 months ago

Hi,
up to now, most detailed spec of HDL support for Quartus was available in Quartus help file. While Quartus pro has updated help for V 24.3, Quartus Std/Lite seems to be stuck at help for V 18.1 which is still delivered with most recent version. I conclude that no functional changes or enhancements took place since then. Is it true?

Generally, I remember it has been stated that Quartus Std./Lite has limited language support compared to Pro. Would be interesting to hear about plans for improvement.
Regards
Frank