SystemVerilog logic type as bidir

Hello,

I'm new to SystemVerilog and have a question about a warning Quartus is throwing. I'm working with a design done by someone else.

In my code I have a 2 interfaces which have port type logic. In the module there is assignment of one logic type to another... for example

interface typeA();

logic[3:0][3:0] mem_A;

endinterface

interface typeB();

logic[3:0] b1;

logic[3:0] b2;

logic[3:0] b3;

endinterface

module dut(typeA in, typeB out);

assign out.b1[0] = in.mem_A[0];

assign out.b2[1] = in.mem_A[1];

assign out.b3[2] = in.mem_A[2];

endmodule

I'm trying to get rid of this warning but don't know what do to since the interfaces are being used multiple times all over the design.

Warning (10665): Bidirectional port "IN.pix[0][2]" at If.sv(47) has a one-way connection to bidirectional port "OUT.grn[0][2]"

Thanks in advance.