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Honored Contributor
Honored ContributorSystemVerilog logic type as bidir
Hello, I'm new to SystemVerilog and have a question about a warning Quartus is throwing. I'm working with a design done by someone else. In my code I have a 2 interfaces which have port type ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The error message has the identifiers 'pix' and 'grn', but they do not exist in the source code. --- Quote End --- The code is just an example...the warning is copied from Quartus. In all correctness the warning to match example should have been Warning (10665): Bidirectional port "in.mem_A[0][0]" at If.sv(#) has a one-way connection to bidirectional port "out.b1[0][0]" Warning (10665): Bidirectional port "in.mem_A[0][1]" at If.sv(#) has a one-way connection to bidirectional port "out.b1[0][1]" Warning (10665): Bidirectional port "in.mem_A[0][2]" at If.sv(#) has a one-way connection to bidirectional port "out.b1[0][2]"
