Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

SystemVerilog logic type as bidir

Hello, I'm new to SystemVerilog and have a question about a warning Quartus is throwing. I'm working with a design done by someone else. In my code I have a 2 interfaces which have port type ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The error message has the identifiers 'pix' and 'grn', but they do not exist in the source code.