SystemVerilog logic type as bidir

Hi,

--- Quote Start ---

interface typeA();

logic[3:0][3:0] mem_A;

endinterface

interface typeB();

logic[3:0] b1;

logic[3:0] b2;

logic[3:0] b3;

endinterface

module dut(typeA in, typeB out);

assign out.b1[0] = in.mem_A[0];

assign out.b2[1] = in.mem_A[1];

assign out.b3[2] = in.mem_A[2];

endmodule.

--- Quote End ---

Don`t you think that, here you are trying to access one interface members by another interface since an interface is a bundle of nets or variables & interface construct in system verilog was specifically created to encapsulate the communication between blocks or modules.

Refer the attached pdf. for detail about an interface.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)