Altera_Forum
Honored Contributor
7 years agoSystem Verilog Pin Assignment Issues
Newbie question - Just bought my first FPGA and working through examples to understand design and coding. My first example using a block diagram and .v file worked fine. My next try was using a book that has System Verilog examples. When entering System Verilog coding and going to Pin Planner in Quartus Prime 18 (Lite Edition), the pin definitions are not the same and not correct. Any idea what I am doing wrong? Same device number was used.