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Altera_Forum
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7 years ago

System Verilog 2009 Generate Loop

How can I get this piece of code to compile? This works fine in other synthesis tools, simulation etc. Just trying to map it to an FPGA. In Quartus 17.1 and 18.0 I get this error: Err...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Usually when you get an unexplainable syntax error, there is a problem with the code just before it.

SystemVerilog added the ability to put the genvar inside the for loop. Verilog-2005 made the generate/endgenerate keywords optional. The compiler should be able to tell from the context whether the for-loop is a generate-for or a procedural-for. I would try removing them and seeing if you get a different error message.